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P2010 - PLLs problem

Question asked by Marco Santos on Apr 10, 2013
Latest reply on Jun 21, 2013 by Marco Santos

In my board, the P2010 has problems with the internal PLLs. The SYSCLK is 66.6666MHz and the CCB ratio is 8:1 but I get about 1GHz at the CLK_OUT pin if I select in GUTS_CLKOCR=0x80000000. What is even more strange is the I got about 58MHz at CLK_OUT pin if I choose GUTS_CLKOCR=0x80000003 and not 33MHz. What is even more stange is that the 8:1 ratio of the CCB should be 533MHz (8x66=533) but if I choose the 4:1 CCB ratio I got 533MHz! Another very strange thing is that the GUTS_PORPLLSR register shows correct ratios but the clocks doesn't match what the register says. But, the GUTS_PORPLLSR register also has some strange things. In the reference manual the figure of this register shows 5 bits for the DDR_RATIO but the describing text shows 6 bits.

Anyone where experience a similar problem? I already check every clock, voltage and bootstrap and every thing looks okay.

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