I am gaining experience with working with the NAND controller but noticed the following:
- when data is written to a page with 32-error correction (writing 60 ECC bytes to the spare area) it reads back normally
- if however a block is erased and the content read the content returned is not completely 0xff, but the byte at offset 0x5fd in the page buffer (2k page mode) is read as 0xdf. That means that one bit is at '0'
- if the erased block is read with error correction disabled all of the content is read as 0xff, showing that the bit is inverted by the ECC trying to correct an error.
My question is how can software best identify an erased page as being all 0xff ? A standard blank check on the memory fails due to the single '0' so should the ECC status be used, or the fact that the 60 bytes in spare area which would be used for ECC are all 0x00? Or perhaps a different ECC is preferred to avoid this?
Finally, is this behaviour actually normal? I have used a "less powerful" NAND controller with a smaller NAND device (with 512 byte pages) and don't remember such a difficulty.