AnsweredAssumed Answered

i.MX28 DDR2 SDRAM address space mapping (esp. chip select mapping)

Question asked by Dimitar Boevski on Mar 18, 2013
Latest reply on Mar 24, 2013 by Yuri Muhin
Branched to a new discussion

Hello engineers :-)

I have a strange issue.

I have one DDR2 memory chip with 13 address pins, 10 column pins, 8 banks and 16-bit width.

As far as I understand the manual my register configuration should be:



COLUMN_SIZE=0x2  // 12 - 2 = 10

ADDR_PINS=0x2  // 15 - 2 =13




and of course lots of other registers, but the above are the ones i'm currently interested in.  I have disabled the EMI_CE1N pin and disabled the last two address pins. The above configuration doesn't work but as soon as i change CS_MAP to 0xf it works! How come? I have one chip only. My EMI_CE0N pin is connected to the memory chip select, the EMI_CE1N pin is not connected at all. How come mapping over nonexistent chip selects works while the correct configuration doesn't, what am I missing?

Besides, i don't get it how CS_MAP allows for a value of 0xf for enabling the mapping of 4 chip selects when the i.MX28 has only two chip selects on the EMI interface?! Where are the other two chip selects?