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9s12xs ATD setup

Question asked by Robert Haines on Mar 17, 2013
Latest reply on Mar 24, 2013 by Robert Haines

Thanks in advance for answering what appears to be a basic question:

 

I've had some difficulty setting the ATD pins on my 9s12xs128.  My goal is to get all 16 pins set to A/D each to read a separate input.  However, after spending days changing one setting at a time, I'm starting to wonder if the chip is bad.  So, before I throw this one in the trash, please someone check my settings.

 

Here's the code (all other ATD settings are at their default):

 

ATD0CTL1_SMP_DIS  = 0;   // Discharge the pin prior to a reading

ATD0CTL1_SRES1    = 1;   // Sets to 12-bit resolution (default is 10-bit)
ATD0CTL1_SRES0    = 0;
ATD0CTL2_AFFC     = 1;   // Sets to Fast Flag Clear
ATD0CTL3_DJM      = 1;   // Right Justified
ATD0CTL3_S8C      = 0;   // 1 Conversion per sequence
ATD0CTL3_S4C      = 0;
ATD0CTL3_S2C      = 0;
ATD0CTL3_S1C      = 1;
ATD0CTL4_SMP2     = 1;   // 24 Clock cycles per scan
ATD0CTL4_SMP1     = 1;         
ATD0CTL4_SMP0     = 1;
ATD0CTL4_PRS      = 1;   // ATDCLK = 20mHz / (2 x (1+1)) = 5mHz [buss is at 20mHz]
ATD0CTL5_SCAN     = 1;   // Continuously scan
ATD0CTL5_MULT     = 1;   // Scan all channels

 

Now, when I put a few volts on any of the pins I get no readings.

 

I've also changed it to 16 conversions per sequence and tested pin ATD0 (I would expect it to read that pin 16 times) and what I get is registers ATD0DR0 through ATD0DR5 at 0000, ATD0DR6 and ATD0DR7 with a value that I can change switching the input voltage on and off (and the values do not match the voltage ratio), and ATD0DR8 through ATD0DR15 at 4095.  This at least lets me know that physically have it connected, but the results are confusing.

 

Also, if anyone has a simple C program I could load in CodeWarrior just to setup and test the ATD system, I would be happy to try it.

 

Please help and Thanks!

 

Robert

 

Adapt9s12sx breakout board from Technological Arts.

CodeWarrior 5.9.0

Connected by USB through a USBDM / TBDML

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