I am designing a new device, and plan to use the MK20DX64VLH7 Kinetis MUC. This system need 256kB external SRAM.
I have read the thread K20 external memory interface description wanted. But still not absolute sure. From the datasheet of the MK20DX64VLH7, there are FB_AD[17:0], FB_RW, FB_ALE/CS1/TS, FB_CS0#.
The SRAM Chip have A[17:0], D[15:0], WE#, OE#, CS1# and CS2.
Can i use that SRAM in multiplexed mode, by
latching the FB_AD[17:0] to SRAM_A[17:0],
FB_AD[15:0] to SRAM_D[15:0],
FB_RW to SRAM_WE#,
FB_ALE to the latched_FB_AD[17:0]
FB_CS0 to SRAM_CS0#?
Or do i any more glue logic? In the link above, the FB_AD[31:16] are used for data bus, but those pins are not available on the 64pin MK20DX64VLH7.
For this K20 device, the Fsys frequency is 36MHz. What could i expect as burst read/write rate? Considered the SRAM fast enough, are additional wait states required?
Any help or shared experiences with a multiplexed SRAM on the Kinetis would be helpful.