I'm trying to implement a 16 bit pwm by using emios on a MPC563x. The PWM frequency is to have 100 kHz, the system frequency is given with 80MHz. Reading all the official examples I'm somehow stuck how to continue on that matter.
Initializing the emios module and setting up a pwm with a given frequency works well.
EMIOS.MCR.B.GPRE= 7; /* Divide 80 MHz sysclk by 7+1 = 10 for 10MHz eMIOS clk*/
EMIOS.MCR.B.ETB = 0; /* External time base is disabled */
EMIOS.MCR.B.GPREN = 1; /* Enable eMIOS clock */
EMIOS.MCR.B.GTBE = 1; /* Enable global time base */
EMIOS.MCR.B.FRZ = 1; /* Enable stopping channels when in debug mode */
/* EMIOS CH 2: Output Pulse Width & Freq Modulation*/
/* Provide 100kHz output (10usec period) */
/* Input clock is eMIOS clk of 10MHz (0.1 usec period)*/
EMIOS.CH.CBDR.R = 99; /* Period = 0.1 usec x (99+1) = 10 usec, 100kHz*/
EMIOS.CH.CADR.R = 19; /* Duty cycle = 0.1 usec x (19+1) = 2 usec (20%) */
EMIOS.CH.CCR.B.UCPRE = 0; /* Channel counter uses divide by (0+1) prescaler */
EMIOS.CH.CCR.B.UCPREN = 1; /* Channel counter's prescaler is loaded & enabled*/
EMIOS.CH.CCR.B.EDPOL = 1; /* Polarity is active high */
EMIOS.CH.CCR.B.MODE= 0x19; /* Mode= 0PWFM, next period update, flag on B match*/
SIU.PCR.B.PA = 3; /* Initialize pad for eMIOS channel. */
SIU.PCR.B.OBE = 1; /* Initialize pad AC16 for output */
But how to include a variable 16 bit duty cycle by keeping the same frequency? The system clk is divided and results in the emios clk. The latter, is used to increment until the value of register CBDR is reached. When this is true, CBDR should have a value of 2^16. When doing so the required sys clk increases dramatically. So where's the solution? Am I missing something completely?