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[K60_120] Make 120MHz sysclk and independent audio clock with PLL0/1

Question asked by harukihasegawa on Mar 8, 2013
Latest reply on Mar 21, 2013 by harukihasegawa

Hello,

 

I'm designing a product which uses Kinetis K60_120 series MCU.

The product has a I2S audio output and high-speed USB interface.

 

I have two questions about system/audio clocking.

Figure 1 shows a summary of device clocking. I want to make both audio and system/USB clock from one 12MHz crystal.

 

figure1.png

Figure 1: Summary system clocking diagram

 

Question 1: Does the PLL can make 120MHz output from 12MHz crystal?

 

Figure 2 is a MCG block diagram extracted from reference manual.

The f_pll_ref and f_vcoclk_2x symbols are described on 'Table 15. MCG specifications' from datasheet.

 

K60 datasheet says, the valid frequency range of each signals are;

f_pll_ref:   8 MHz - 16Mhz

f_vcoclk_2x: 180 MHz - 360MHz

 

Now, we can make 120MHz from 12MHz with PRDIV0 = 2, VDIV0=20 settings.

 

MCGPLL0CLK = 12MHz / 2 * 20 / 2 * 2 = 120MHz

f_pll_ref = 12MHz / 2 = 6MHz (!!!)

f_vcoclk_2x = 240MHz

 

As you can see, f_pll_ref does NOT meet the constranits described on datasheet.

Can I get 120MHz system clock from 12MHz crystal?

 

figure2.png

Figure2: MCG block diagram

 

 

Question 2: Does the PLL1 can be used as a independent audio clock source for I2S/SAI module?

 

I want to make audio clock with PLL1 which is independent of system clock.

 

Figure 3 is a I2S/SAI clocking diagram of K60_100 series MCU. 'MCGPLLCLK' is connected to I2S/SAI module.

 

Figure 4 is K60_120 series MCU's one. Same 'MCGPLLCLK' is connected to I2S/SAI module, but it is not drawn in the MCG diagram.

I guess 'MCGPLLCLK' signal is a output of PLL0/1 selector. (But it means I can't get independent audio clock from PLL1..)

 

figure3.png

Figure 3: I2S/SAI clocking diagram of K60_100

 

figure4.png

Figure 4: I2S/SAI clocking diagram of K60_120/150

 

Regards,

Haruki Hasegawa

 

 

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