I am running code from sysRAM using Cortex-A5 alone with MMU/caches disabled. I get alignment fault data abort when accessing (store instruction) sysRAM memory from strcat() that is not aligned on word boundary. I have following questions regarding this issue:
1- Doesn't the processor support unaligned sysRAM memory access even when I have A bit cleared in SCTLR register. Is there any cortex-A5 specific configured required?
2- Is sysRAM on this target un-cacheable. Moreover, can I enable MMU with translation table placed on sysRAM? Currently I am unable to enable MMU from sysRAM.
Solution that can allow hardware unaligned access for sysRAM is preferred rather than needing to change code or using compiler alignment flags. Or I will have to enable externa DDR and then MMU to get rid of these issue?