We are currently working to handle the CAN bus off condition when using 9S08DV32 and request you help in implementing the same.
According to the CAN specification, after CAN bus off condition, the node has to wait for 128 occurrences of 11 consecutive recessive bits.
Can anyone throw some light on
i) How to handle the bus-off recovery condition in this processor?
ii)What registers must be altered and in what order when a bus off condition occurs?
Added part number to subject.
Message Edited by NLFSJ on 2007-07-04 09:19 AM