In the i.MX 6Dual/6Quad Applications Processor Reference Manual (Document Number: IMX6DQRM, Rev. 0, 11/2012), a pad (RESET_IN_B) is called out in section 10.4.1.4.3.3. It mentions that one can turn on and off the PMIC supplies to the SoC by setting SNVS_LP DP_EN to “1” which allows access to the PMIC_ON_REQ pad directly. I can find no such pad (RESET_IN_B), nor can I find SNVS_LP DP_EN. This pad (RESET_IN_B) is also referenced in section 11.4.2 as being the pad to which the on/off button should be attached. Is it safe to assume it should be attached to the ONOFF pad instead?
I would like to be able to have the SoC control the PMIC (so it can execute the low power modes), but also be able to use a button to force a hard reset (as mentioned in section 59.2.1) should the SoC become unresponsive. I am using the PF0100 as the PMIC and cannot determine by which method described in section 59 this can be accomplished.
On both Figure 59-2 and 59-3 (IMX6DQRM) there is an input called RST that is NAND’d and NOR’d with the ONOFF input. To what PAD or signal does this connect?
Assume the PMIC has been connected as suggested in IMX6DQSDLHDG (Hardware Development Guide for i.MX6), Rev0, 10/2012. The PF0100 defaults to PWRON_CFG = 0, the level trigger, but in the Power Mode transitions table 59-1 (IMX6DQRM) detailing the flow with the PMU in control, it appears that all of the behavior of the SoC when it is in control is assuming that the PF0100 has PWRON_CFG=1. Is this true?
In the "Emergency On to OFF by button", Table 59-1 (IMX6DQRM), (which is the case in which I am most interested) #3 implies that a ‘1’ on pmic_en_b will turn off the PF0100. This can only be true if the button press (to GND) has been routed through to the PMIC_ON_REQ pad so that the output to the PF0100 has been held low for longer than 4 seconds. Is this true? Does this behavior require any special register control (i.e. the previously mentioned difficult to find SNVS_LP DP_EN)?
I would love to know how to get a PMIC and iMX6 which are both in deep sleep modes to perform a power-on-reset.