No signals on CS and CLK after DDR3 configuration

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No signals on CS and CLK after DDR3 configuration

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kalmanh_
Contributor I

I am working on a designed board where 128MB DDR3 memory and MX6Q processor are implemented. I tried to configure MMDC registers for u-boot2012.11 by the reference manual (MMDC initialization) , but after start no measurable signals are found in the chip select and the clock lines of DDR3 module. I am able to set/read registers, and I also can turn on/off a LED by GPIO registers.

My question is shouldn't I measure any signal on the listed lines? It can happen I configured it a wrong way, but in my opinion I should see some signals on those lines in case of errors also.

I also tried to use some other definitions which works well with development boards but I got the same result on my board.

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LinWang
NXP Employee
NXP Employee

Hello,

Not sure if it is too late to follow your question now.

I am involved into this DI just now.

Please find and check below two DDR script aid and tool first.

i.MX6 DDR Stress Test Tool

https://community.freescale.com/docs/DOC-96412

i.Mx6DQSDL DDR3 Script Aid

https://community.freescale.com/docs/DOC-94917

If you also have issue after applying above, schemaic and layout should be reviewed.

Hope above infocan help you!

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LinWang
NXP Employee
NXP Employee

Hello,

Not sure if it is too late to follow your question now.

I am involved into this DI just now.

Please find and check below two DDR script aid and tool first.

i.MX6 DDR Stress Test Tool

https://community.freescale.com/docs/DOC-96412

i.Mx6DQSDL DDR3 Script Aid

https://community.freescale.com/docs/DOC-94917

If you also have issue after applying above, schemaic and layout should be reviewed.

Hope above infocan help you!

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