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MPC8548 not executing code from DDR

Question asked by Ravindra Kulkarni on Feb 8, 2013
Latest reply on Apr 10, 2013 by lunminliang

Hi

I am using u-boot (2010.09) and the processor does not execute the code from the DDR.

Please help.

 

I am using CW USB TAP for debugging.

Details follow.

The code executes all the way up to th point that it copies itself into the DDR ( on DDR interface , not on LBC), and the copy is correct.

As soon as it executes the blr instruction, the PC changes to DDR address (0x00370000, I am using 4Mbytes of DDR for now), and either it hangs or after doing a single step, the PC increments but does not do anything with the registers.

 

The ddr is solid and I can execute code from DDR independently, (Welcome to Code Warrior sample application)

ALso please see the uboot messages  (IGNORE the clocks for now, I have forcefully populated the clocks but has nothing to do with real hardware)

The internal clock is at 400 MHZ.

 

It seems to me like the ICACHE is not working correctly, Some incorrect configuration?

 

The code just above this works fine, it invalidates the D Cache

but not sure about I Cache

addi r0,r10,in_ram - _start + _START_OFFSET
mtlr r0
blr    /* NEVER RETURNS! */   HANGS AFTER THIS
.globl in_ram
in_ram:

/*
  * Relocation Function, r12 point to got2+0x8000
  *
  * Adjust got2 pointers, no need to check for 0, this code
  * already puts a few entries in the table.
  */
li r0,__got2_entries@sectoff@l

 

 

u-boot messages

U-Boot 2010.09 (Feb 07 2013 - 20:17:08)

CPU: 8548E, Version: 3.1, (0x80390031)

Core:  E500, Version: 2.2, (0x80210022)

Clock Configuration:

       CPU0:882.713 MHz,

       CCB:2105.033 MHz,

       DDR:1052.516 MHz (2105.033 MT/s data rate), LBC:263.129 MHz

L1:    D-cache 32 kB enabled

       I-cache 32 kB enabled

CPU Board Revision "my custom board"

I2C:   ready

DRAM:  Initializing

    DDR: 4 MiB (DDR2, 64-bit, CL=2, ECC off)

Top of RAM usable for U-Boot at: 00400000

Reserving 535k for U-Boot at: 00370000

Reserving 80 Bytes for Board Info at: 0034dfb0

Reserving 76 Bytes for Global Data at: 0034df64

Stack Pointer at: 0034df48

New Stack Pointer is: 0034df48

Relocation address at: 00370000

 

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