Franz Huber

MPC5602B: Timing information needed on setting EHV-bit in FLASH_MCR

Discussion created by Franz Huber on Feb 8, 2013
Latest reply on May 28, 2013 by Lukas Zadrapa

Hi all,


one urgent question about delay/stall of program-execution on first time setting the EHV-bit to initiate erase/write of flash.


Following setup of the hardware:


- External watchdog with fixed cycle-time of 200ms (can't be changed)


Now, on setting the EHV-bit it looks like the processor is going into a "stall" for longer than 200ms leading to a reset by the watchdog.


Has anybody else experienced this behaviour and maybe a workaround for this?


Kind regards