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MCF51QU64 - Wakeup through LPTMR from VLLS3 mode

Question asked by vani on Feb 2, 2013
Latest reply on Feb 4, 2013 by TomE

Hi All,

 

    This is regarding wakeup functionality of MCF51QU64. In our application, we are using LPTMR 0 to wakeup from VLLS3 mode.

 

OSC clock used for LPTMR and ERCLKEN, EREFSETN bit settings made to work during STOP mode.


To enter into VLLS3 following settings made:

PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,

VLLSCTRL[VLLSM]=x (VLLSx), STOPE=1, WAITE=0

STOP instruction issued

 

 

To wakeup, following setting is being used:

  /* Enable LPtmr0 as wake up source for Very Low Leakage Wake Up */

  LLWU_ME |= 0x01;

 

The processor is not waking up from this mode. But LPTMR is working as expected and code written in such a way that if it comes out of VLLs3 mode,clock settings are reinitialized.

Are there any setting missing with respect to wakeup?

 

If we configure it to wake up from LLS mode, then the processor is waking up(not with VLLs3).

 

Regards

Vani

 

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