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i.MX51 disable interrupts

Question asked by George Fukutomi on Jan 30, 2013
Latest reply on Feb 4, 2013 by jimmychan
Branched to a new discussion

Hi all,


Please let me know about interruption of i.MX51.


When disabling interrupts, should I-bit of the CPSR register of ARM core be set to DISABLE?

Or is anything alse needed?


GPIO interrupt occurs I-bit in set to DISABLE.

* Trust Zone Interrupt Contoller is ENABLE and F-bit of CPSR register are ENABLE.


Please give some ideas.


Best Regards,