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Strange conflict between CG5 (ethernet clk) and CG0 (ECSPI1 clk)...

Question asked by Ed Sutter on Jan 21, 2013
Latest reply on Jan 31, 2013 by Ed Sutter
Branched to a new discussion

For the last few days I've been working on an SPI-nor-flash driver on the MX6Q-SDB Sabre Smart Devices board.

Part of that initialization is to set the two CG0 bits in CCM_CCGR1; however, I'm noticing that when I do

that with a read/modify/write (ORing the register with 0x3) my ethernet interface stops working.  To get

around this I OR the register with 0x0c03 (which includes the CG5 bits for ethernet).  It appears that when I

set the CG0 bits of CCM_CCGR1, that causes the CG5 bits to need to be set again.

Any idea why I should have to do that?