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i.MX53 SSI problem

Question asked by alexeryomenko on Jan 17, 2013
Latest reply on Jun 24, 2015 by caleb crome

Hello!

 

I am developing driver for the TDM network of 8 DSPs now. That's why I configured SSI with 8 timeslots. I have problem with synchronizing DMA with SSI: start of the DMA chunk occupies random slot of SSI.

My sequence of configuration:

1. Configure DMA transfers (MXC_DMA_SSI2_8BIT_TX0 and MXC_DMA_SSI2_8BIT_RX0).

2. Configure SSI in network mode (8 timeslots, 8 bits, single bit FSYNC from external clock) for both RX and TX paths.

3. Enable SSI, because I need to produce FSYNC from external clock to initialize DSPs correctly.

4. Enable DMA transfers.

5. Enable RX and TX paths of SSI.

 

In spite of this sequecnce, I have no synchronization between DMA and SSI.

Can any one help me with my problem? May be someone have experience with same problem?

 

 

 

Thank you in advance!

 


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