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i.mx53 ddr3 setting

Question asked by Max Chou on Jan 10, 2013
Latest reply on May 18, 2013 by grantw
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Hi  All

 

I had a question about i.mx53 DDR3 ZQ setting,

in i.mx53_smd flash_header.S

MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x724, 0x04000000)

The ddr_sel is "10"

but I can find two different description in i.mx53RM,

the smd schematic use 240 ohm ZQ resitor, 

which DDR_SEL value is correct?? "00" or "10"

 

 

Table 43-2. DDR Output Driver Average Impedance

未命名2.bmp

IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE field descriptions

未命名1.JPG

 

Sincerely, Max

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