AnsweredAssumed Answered

32bit bus width memory with 2 cs in IMX6Q

Question asked by stevetsai on Dec 30, 2012
Latest reply on May 17, 2013 by stevetsai
Branched to a new discussion

I am porting software with a board using IMX6Q which built in 2GB DDR3 memory.  The board uses 32 bits memory bus instead of 64 bits memory bus, and it uses two CS signals to select these chips. I can setup 32 bits mode with 1GB memory, but I got the problem when I try to use CS1. It means that I can run Linux with 1G memory, but I can not run the kernel with 2G memory. The following are the settings I am using.  Does anyone use the same DDR configuration successfully?

 

 

 

MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)

MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0xC4190000)

MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)

MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)

MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)

MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)

MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)

MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)

MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)

MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)

MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)

MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)

 

Outcomes