I would like to use the MK20 kinetics SPI port configured as a slave to replace two 8-bits serial to parallel shift registers in one of our board.
The existing serial protocol nearly acts as a SPI bus except that before starting data transfer, the read data must be loaded by a pulse on a"LOAD" line and at the end of the transfer the written data must be validated by a pulse on a "STROBE" line (both actions can be handled by external interrupts controlling the DSPI module I suppose ?)
There is one single SPI bus rated at 1.8Mbit/s in which all SPI slaves are connected in series to the Master (no use of chip select forced to"0" state).
So the required sequence is the followed : the Master sends a load pulse trough an external interrupt and the UC loads data's in TXFIFO of DSPI (2 Bytes). Then the SPI transfer begin (activity on clock SPI) and data's are received by the DSPI configured as slave. The thing is 20 Bytes are sent continuously from the master to the slave butfor the DSPI module only the 2 first(TX DATA to master) and the 2 last Bytes(RX DATA from master) are relevant.
The remaining 16 Bytes between just have to pass through the shift register and be sent to the SDO output for other SPI slaves.
So my questions are :
- What are the data's sent out on clock SPI activity when the TX FIFO is empty ?
- Does a Transmit FIFO Underflow Flag will affect the behavior of DSPI module or it just can be ignored ?
- Is it easy to setup a DMA mechanism in reception in order to prevent too much interrupt to CPU coming from the SPI bus ?
thanks for the support