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mx50 EIM_BCLK problems and WEIM_BASE_ADDR

Question asked by jayakumar2 on Dec 15, 2012
Latest reply on May 1, 2013 by GraceH
Branched to a new discussion

Hi freescale friends,

 

I'm working with a i.mx508 board, very similar to the RD3 board. I've been trying to get an fpga interfaced on CS1 and hitting a set of problems. Here are the details:

a) WEIM_BASE_ADDR

In the 2.6.35.3 release, the code says:

arch/arm/plat-mxc/include/mach/mx5x.h:

#define WEIM_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DA000)

 

That seems incorrect to me because IMX50RM.pdf shows that WEIM is at:

Addresses: EIM_CS0GCR1 is 63FD_8000h base + 0h offset = 63FD_8000h

(page 1135)

 

but if I change the value of WEIM_BASE_ADDR in mx5x.h to be + 0xD8000, I then get an unhandled fault upon read access of that address/register.

XXXjaya reached setup_cs1:2399 weimbase physical=0x63fd8000

XXXjaya reached setup_cs1:2400 weimbase ioremap=0xa086e000

XXXjaya reached setup_cs1:2420

Unhandled fault: external abort on non-linefetch (0x008) at 0xa086e000


where the code was:

 

weim_base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K);

        printk(KERN_INFO "XXXjaya reached %s:%d weimbase physical=0x%x\n", __func__, __LINE__, MX53_BASE_ADDR(WEIM_BASE_ADDR));

        printk(KERN_INFO "XXXjaya reached %s:%d weimbase ioremap=0x%p\n", __func__, __LINE__, weim_base);

    reg = readl(weim_base + 0x0);
    printk(KERN_INFO "XXXjaya %s:%d EIM base=0x%x\n", __func__, __LINE__, reg)

btw, I'm using the MX53_BASE_ADDR macro there because the mx5x.h header has its AIPS2_BASE_ADDR as + 0x2000_0000 of the actual value.


Anyone have any ideas why I'm getting a unhandled fault? Looking at mm.c, it looks like this range has a valid 1MB mapping setup.

 

b) If I leave WEIM_BASE alone, ie: to get 0x63FD_A000, then when I set the registers using:

ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K);

    __raw_writel(0x0021008F, weim_base + 0x18);
    __raw_writel(0x00001000, weim_base + 0x1C);
    __raw_writel(0x0C300010, weim_base + 0x20);
    __raw_writel(0x00000008, weim_base + 0x24);
    __raw_writel(0x08600008, weim_base + 0x28);
    __raw_writel(0x00000000, weim_base + 0x2C);

 

The register writes succeed and I can read them back. When I test with this, I see EIM_CS1 assert, EIM_LBA and EIM_RW too when I do a userspace 32-bit read from 0xF400_0000 (via mmap of /dev/mem). But EIM_BCLK does not get driven. I've tried various settings for the EIM config registers, eg: BCM/SRW/SRD and not getting BCLK at all. My guess is that since WEIM_BASE is wrong in mx5x.h, I'm just getting the default behavior for WEIM which might be one where BCLK doesn't get asserted.

 

btw, I've enabled weim_clk and it shows up in /proc/cpu/clocks.


root@freescale ~$ cat /proc/cpu/clocks | grep -i eim

weim_clk1-0                         ______    2    66666666 (66MHz)
weim_clk-0                          PA____    1   133333333 (133MHz)


I'd appreciate any advice on what to look at or debug. If anyone could confirm that EIM_BCLK should assert for a 32-bit read/write, that would also be useful.


Thanks,

jaya

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