we are in the conceptional phase of a i.MX6 based design. Our customer wants to use a NOR-Flash as primary boot device but we also need an CSI-port with 20-bit, so the only possible solution I see (caused by IOMUX limitations) is to connect the NOR-flash in a muxed manner to the proceesor EIM-port with an external address latch. In addition to this we want to connect a CPLD to the BootConfig-pins to have flexibility in configuring the design to different boot sources.
My plan is to use the CPLD as address latch because the BootConfig1+2-pins are the multiplexed address/data signals too. But to get this to work I need an indication of when the CPU sampled the boot configuration and it is safe to switch the CPLD from configuration- to address-latching-mode. I see in the i.MX6 Reference Manual that there is a feature called "BOOT_MODE-Inversion" (IMX6DQRM.pdf Re. 0, page 5010). As I understand, the CPU outputs the inverted value of the sampled BOOT_MODE on the BOOT_MODE-pins when the sampling of the boot configuration was done. Am I right with this??? Is there another possible solution to see when the processor finished sampling the boot configuration???
On the Freescale i.MX6-SABRE reference design schematic I see that the BOOT_MODE-pins are shorted to VSNVS_3V0 which will cause high currents when the CPU tries to output a '0' on this pins because of BOOT_MODE-Inversion. Is the BOOT_MODE-Inversion implemented in the i.MX6_CPU's as described in the reference manual??? Has someone checked this out??? Maybe someone with a i.MX6-SABRE board on his desk can check it out by changing R106 from 0 ohm to about 1k ohm and measure the voltage on the BOOT_MODE1 after the device booted up (if the voltage on BOOT_MODE1 is 0V after boot has finished the feature should work as described)???
Thanks a lot in advance.