Hi,

I am using iMX6S with a 4Gb Toshiba NAND. It has 4320 bytes per page in which 4096 bytes is for main memory and 224 bytes for spare area.

The NAND require 4 bit ECC for each 512Bytes and the NAND layout is configured with 512Bytes data followed by 26Bytes of spare area.

I have doubts on the ECC correction level to use.

1. I understand I can use 2, 4, 6... bits of ECC correction level. How can I calculate what is the maximum / minimum correction level based on my NAND layout? Where can I find the documentation to calculate this?

2. What is the best correction level? Is it true that the higher level will be better? What is the advantages/disadvantages?

THANKS!

You may refer to the subsection "Determining the ECC layout for a device" under the large section "40 BIT Correcting ECC Accelerator (BCH)" in reference manual to find out the maximum correction level can be used.

For a NAND with 4320 bytes per page, there are 8 x 512 data block and 224 bytes spare area. Because the number of ECC bits requires for a 512 byte data block is (ECC_correction_level * 13 bits), a maximum ECC correction level = 16 can be chosen in theory. In practice, some bytes in spare area are reserved as metadata with checksum and thus a lower ECC correction level will be used.

The higher ECC correction level, the more robust the system can tolerent to bit error. Since the ECC calculation and correction are done by the BCH hardware accelerator, the difference between ECC correction levels is insignificant when comparing to the duration for read/write 1 NAND page. It is always the spare area in one page to determine the ECC correction level.