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ECC Correction level settings

Question asked by kewl on Nov 16, 2012
Latest reply on Mar 27, 2013 by PeterChan
Branched to a new discussion



I am using iMX6S with a 4Gb Toshiba NAND. It has 4320 bytes per page in which 4096 bytes is for main memory and 224 bytes for spare area.

The NAND require 4 bit ECC for each 512Bytes and the NAND layout is configured with 512Bytes data followed by 26Bytes of spare area.


I have doubts on the ECC correction level to use.

1. I understand I can use 2, 4, 6... bits of ECC correction level. How can I calculate what is the maximum / minimum correction level based on my NAND layout? Where can I find the documentation to calculate this?

2. What is the best correction level? Is it true that the higher level will be better? What is the advantages/disadvantages?