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Problems with PWM3 & U0CTS GPIOs

Question asked by waynehawthorne on Nov 12, 2012
Latest reply on Nov 12, 2012 by waynehawthorne

Hi, everyone....

 

I've been trying to do something that should be simple but isn't.

I'm trying to drive PWM3 and U0CTS as standard GPIOs on the 5329.

 

There are some difficiencies in the 5329 manual in the GPIO section that aren't helping.

 

I've been able to drive the PWM1 and LCD_CLS GPIOs, and even in doing this required a little guesswork & deduction on the register maps.

 

In table 13-1, the manual describes PWM3 GPIO as PPWM3, and the /U0CTS GPIO as PUARTL3.  The problem is, when you go to the register descriptions for the config registers (PODR, PDDR), there is no indication at which bits are specifically the ones that these GPIOs are assigned.  To drive PWM1 and LCD_CLS, I've made assumptions based on the PPDSDR_x registers which actually show the correct bits. (Ignoring that there's a typo in Figure 13-20...PPWM2 doesn't exist, and it should be PPWM1.)  I've used this code and modified it for PWM3 and /U0CTS by setting and find that this doesn't work.

 

Here's an example of what I've done for the PWM3 configuration (The /U0CTS config is similar, I'll only post PWM3 for brevity):

regPtr = _PSP_GET_IPSBAR();

regPtr->GPIO.PODR_PWM |= MCF5329_GPIO_PIN_3;

regPtr->GPIO.PDDR_PWM |= MCF5329_GPIO_PIN_3;

regPtr->GPIO.PAR_PWM &= ~MCF_GPIO_PAR_PWM_PAR_PWM3(0);

 

while (1)

{

     regPtr->GPIO.PPDSDR_PWM = MCF5329_GPIO_PIN_3;

     _time_delay( 500 );

     regPtr->GPIO.PCLRR_PWM = ~MCF5329_GPIO_PIN_3;

     _time_delay( 500 );    

 

}


So here are my questions:

1) As you can see, I've made the assumption that PWM3 is pin 3 in the PODR and PDDR, since the register maps in the manual (Tables 13-4 and 13-12) don't show the specific pins.  Is this a legit assumption?

2) Has anyone else had any issues with the configuration of /U0CTS or PWM3 as GPIO's?

 

Cheers & Thanks

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