I' m using a tower modul with a K20 72MHz MCU and i would like to use the ADC.
I've got the following questions:
CFG2[ADHSC] is used to configure a higher clock input frequency. This will allow
faster overall conversion times. To meet internal ADC timing requirements,
CFG2[ADHSC] adds additional ADCK cycles. Conversions with CFG2[ADHSC]=1 take
two more ADCK cycles. CFG2[ADHSC] must be used when the ADCLK exceeds the
limit for CFG2[ADHSC]=0.
From which ADCK upwards it must be set? I didnt found that in the manual
After a reset what is the normal clock speed of everything?
Something like that:
Core clock 72 MHz
System clock 72 MHz
Bus clock 36 MHz
FlexBus clock 36 MHz
Flash clock 24 MHz
Am I right with that? Thanks in advance for your answer.