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K70 Tower USB MSD Bootloader problems

Question asked by Tom Junkans on Oct 24, 2012
Latest reply on Dec 6, 2012 by Monica Arvizu

I am having problems with the USB MSD bootloader working on a K70 Tower System.  I Have this code working on a K40 and a K60 tower. I am attempting to use the 50Mhz clock tied to PTA18 as an external reference clock, just like the K60.

 

My problem is in the pll_init() function, after I set MCG_C2 = 0; which should request the external reference clock, then when I wait for the MCG_S to signal the FLL source is the external reference clock, but that never happens. 

 

I never break out of this loop --> while (MCG_S & MCG_S_IREFST_MASK){};

 

Below is my pll_init() code ported from K60 to the K70. If anyone can see what the hey my problem is or has any ideas, that would be super.

 

Thanks in advance and cheers.

 

static unsigned char pll_init()

{     

          /*This assumes that the MCG is in default FEI mode out of reset. */

          /* First move to FBE mode */

          /* Enable external reference clock, RANGE=0, HGO=, EREFS=, LP=, IRCS= */

    MCG_C2 = 0;

           // Select external reference clock and reference Divider 

           // and clear IREFS to start ext osc

           // CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0

    MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);

  

         /* wait for Reference clock Status bit to clear */

     while (MCG_S & MCG_S_IREFST_MASK){};

       /* Wait for clock status bits to show clock source is ext ref clk */

      while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){};

 

    MCG_C5 = MCG_C5_PRDIV0(7);       // (BSP_REF_CLOCK_DIV - 1); == 24

 

             // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled,

      // PLL enabled, clk monitor disabled, PLL VCO divider is clear 

    MCG_C6 = 0;

 

        /* Set system options dividers */

    SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) |  /* core/system clock */

                  SIM_CLKDIV1_OUTDIV2(0) |  /* peripheral clock; */

                  SIM_CLKDIV1_OUTDIV3(0) |  /* FlexBus clock driven ext pin*/

                  SIM_CLKDIV1_OUTDIV4(1);   /* flash clock */

    

    /* Set the VCO divider and enable the PLL, LOLIE = 0, PLLS = 1, CME = 0, VDIV = */

    MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0); /* 2MHz * BSP_CLOCK_MUL */

 

    while (!(MCG_S & MCG_S_PLLST_MASK)){}; /* wait for PLL status bit to set */

    while (!(MCG_S & MCG_S_LOCK0_MASK)){}; /* Wait for LOCK bit to set */

 

        // Transition into PEE by setting CLKS to 0

    // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0 

   MCG_C1 &= ~MCG_C1_CLKS_MASK;

 

          /* Wait for clock status bits to update */

    while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};

 

    return 0;

}

 

 

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