I'd like to periodically trigger a DMA SPI TX transfer. Of course this is easily achieved with a timer, DMA with major loop set to the sequence length, and an interrupt routine that writes to the SERQ register to start a DMA. But I would like to do it using no CPU intervention.
So it looks like I can make use of the PIT and DMA triggering capability. However, if I understand section "21.4.1 DMA channels with periodic triggering capability" and Figure 21-54 and 21-55 correctly, the PIT trigger gates the "peripheral request"-->"dma request" such that once the peripheral request deactivates you must wait until the next trigger event to be able to reassert the DMA request from the peripheral request.
Since the DSPI TX has only a four word FIFO this means that I can kick off an SPI DMA transfer, but this is good for only up to four words, upon which time the peripheral request deasserts (FIFO full) until some words are shifted out the SPI. But even after the SPI is ready for more data I will have to wait until the next trigger interval for any more words to get written to the TX FIFO. This seems to limit my periodic transfers to only four words.
So my question is what if I have a long SPI sequence of say 16 words that I want to periodically transfer? Can this be accomplished? If I set my DMA major loop to 16 words, the functionality I really want is to not gate my DMA request with the PIT, but instead have the PIT assert my DMA Start (SERQ). Does this functionality exist?
I see indirect ways to do this, perhaps by linking DMA channels where the PIT would cause a short DMA transfer that links to the SPI DMA of another channel (asserting SERQ) and doing the long transfer. But I'd rather avoid this if possible.