Ive been trying to understand how the P4080 starts up and what things need to be taken care of. Hence I am reading the u-boot source code as well as taking a look at the /arch/powerpc/ directory in the kernel (I am looking at 2.6.27 and 2.6.34 here)
Starting with 2.6.27. So now lets get started to give you all an idea of what am I looking at:
- Under /arch/powerpc/kernel/ I see head_fsl_booke.S which seems to be the first file that the bootloader dives into. Am I right?
- There are some CPU setup functions in the above directory for the 44x series of processors (IBM I believe) as well as the PPC970 but there seems to be none for the e500. So I am guessing the entire CPU setup is happening in the head_fsl_booke.S file. Is it? Where can I get to read the boot startup requirements for freescale devices? Will docs AN3542 and AN3647 suffice or are there other docs that could help? There is a generic app note AN1809 but it seems to be for PPC970 and 'similar devices'. I don't think the P4080(e500) counts as one
- Then Ive been looking at the u-boot code in parallel and it lies here arch/powerpc/cpu/mpc85xx/start.S
- I see that there is a resetvec.S file which branches off unconditionally to _start_e500 which is a section defined in the above file. Now pardon me for being naive, but what exactly does the line .section .bootpg, "ax" tell us? As far as I remember it is naming a certain section as bootpg and that it should be allocatable and executable. Executable I get it, but could folks kindly refresh my memory as why should such a section be allocatable? To allow itself to be re-allocated depending on the memory map of the board?
- Now I a assuming the u-boot has already done many an initialization stuff before handling it over to Linux. Yet I see many similar stuff being done in head_fsl_booke.S. I haven't examined the gritty details of both of them yet but would be great if some one sums the difference in the work done by u-boot and the Linux start up code.
- If I would like to run legacy applications on this system which deal with a 32byte cache line size, I may have to toggle between DCBZ and DCBZL with the latter used to clear the entire default cache line whereas the former clearing only the first 32 bytes (can be done by setting the DCBZ compat bit in L1CSR0 register). Now under the Linux source tree under /arch/powerpc/kernel/ I would like to identify the affected areas. On searching the linux cross reference, I see that those files are
- From above list, the last one is irrelevant but the others I need to be doing exactly what? Replace DCBZ with DCBZL right? But before that, do I need to set the compatibility bit in L1CSR0 in head_fsl_booke.S itself?
I know my post has been really long but I hope I have been clear and succinct in describing what my problem is.
Hoping for an answer.
Thanks in advance