INTERRUPT STACK HANDLING:
I have developed an XGATE SCI(0) Handler. However I am confused about What & How the Interrupt is terminated on exit from XGATE. The Normal Exit of an XGATE Procedure is RTS (RTI is not accepted). With a S9-CPU ISR an RTI re-adjusts the stack and removes the INT from the Interrupt Controller.
1. The Ref manual seems to indicate that the proper procedure is (when exiting from XGATE) is to Interrupt the CPU which would generate an RTI to terminate the INT. I would not wish to do this. Is this the Case?
2. Does the INT Controller properly terminate the Interrupt when the XGATE exits on a RTS?
3. Will the Stack Overflow if the CPU does not issue a RTI ?
It is clear that the CPU has priority over the XGATE and according to the Ref Manual XGATE is 'helded up' (put on hold) until the CPU releases the 'ADDRESS'. Disregarding the SEMAPHORE functions, What does ADDRESS mean.
1. Is it literally each word address? (i.e. the CPU can address $1002 and the XGATE can address $1004 at the same time).
2. If 1 above is not true, what is the Limits of the arbitration scheme.
3. Can anyone referenece a document or explain the speicifics of device arbitration?