Screen is blank for 2 seconds between u-boot bootlogo and kernel penguin

shaojun_wang · ‎10-08-2012

1. Description

In Mx53 SMD, if enable u-boot boot logo, the screen will be blank for about 2 seconds between u-boot boot logo and Kernel penguin.

Below patch can shorten the blank time to less than 1 second. The patch is based on R10.3.2 u-boot and kernel.

In u-boot patch, CONFIG_FB_BASE is changed to 0x8fb00000, which is the physical address of kernel fb0.

To get the address, can printk mxcfb_resources[0].start in fixup_android_board() in kernel_imx/arch/arm/mach-mx5/mx53_smd.c. This address is fixed if pmem, fbmem and gpu_memory in u-boot command line are fixed.

2. u-boot patch

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c

index a7a6fb7..36773f1

--- a/cpu/arm_cortexa8/cpu.c

+++ b/cpu/arm_cortexa8/cpu.c

@@ -141,8 +141,8 @@ int cleanup_before_linux(void)

#endif

#ifdef CONFIG_VIDEO_MX5

- ipu_disable_channel(MEM_BG_SYNC);

- ipu_uninit_channel(MEM_BG_SYNC);

+// ipu_disable_channel(MEM_BG_SYNC);

+// ipu_uninit_channel(MEM_BG_SYNC);

#endif

diff --git a/include/configs/mx53_smd_android.h b/include/configs/mx53_smd_android.h

index b3a91e7..d51d085

--- a/include/configs/mx53_smd_android.h

+++ b/include/configs/mx53_smd_android.h

@@ -336,7 +352,8 @@

#define LCD_BPP LCD_COLOR16

#define CONFIG_CMD_BMP

#define CONFIG_BMP_8BPP

- #define CONFIG_FB_BASE (TEXT_BASE + 0x300000)

+ //#define CONFIG_FB_BASE (TEXT_BASE + 0x300000)

+ #define CONFIG_FB_BASE 0x8fb00000;

3. Kernel patch

diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c

index a57c666..ba76676

--- a/arch/arm/mach-mx5/clock.c

+++ b/arch/arm/mach-mx5/clock.c

@@ -4359,6 +4359,7 @@ static struct clk_lookup lookups[] = {

_REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),

_REGISTER_CLOCK("fec.0", NULL, fec_clk[0]),

_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),

+ _REGISTER_CLOCK("ipg_perclk", NULL, ipg_perclk),

};

static struct clk_lookup mx51_lookups[] = {

@@ -4860,6 +4861,10 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long

clk_tree_init();

+ /* enable pwm_clk */

+ __raw_writel(1 << MXC_CCM_CCGRx_CG7_OFFSET |

+ 3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);

+

for (i = 0; i < ARRAY_SIZE(lookups); i++) {

clkdev_add(&lookups[i]);

mx53_clks[i].reg_clk = lookups[i].clk;

@@ -5034,6 +5039,10 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long

1190000));

base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K);

mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);

+

+ clk_enable(&ipu_clk[0]);

+ clk_enable(&ldb_di_clk[1]);

+

return 0;

}

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c

index dc52165..92808cd

--- a/arch/arm/mach-mx5/cpu.c

+++ b/arch/arm/mach-mx5/cpu.c

@@ -179,10 +179,31 @@ static void __init mipi_hsc_disable(void)

/*!

* This function resets IPU

*/

+#include <mach/iomux-mx53.h>

+#include <mach/gpio.h>

+extern int clk_get_usecount(struct clk *clk);

+extern int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);

+struct timeval ipu_start;

+#define MX53_SMD_GPIO_PWM (0*32 + 1) /* GPIO1_1 */

+EXPORT_SYMBOL(ipu_start);

+

void mx5_ipu_reset(void)

{

u32 *reg;

u32 value;

+ struct clk *ipu_clk;

+

+ printk("%s\n", __func__);

+ mxc_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);

+ gpio_request(MX53_SMD_GPIO_PWM, "gpio_pwm");

+ gpio_direction_output(MX53_SMD_GPIO_PWM, 0);

+

+ do_gettimeofday (&ipu_start);

+

+ ipu_clk = clk_get(NULL, "ipu_clk");

+ if ((ipu_clk != NULL) && (clk_get_usecount(ipu_clk) > 0))

+ clk_disable(ipu_clk);

+

reg = ioremap(MX53_BASE_ADDR(SRC_BASE_ADDR), PAGE_SIZE);

value = __raw_readl(reg);

value = value | 0x8;

diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c

index f28e2e6..5d426ea

--- a/drivers/video/mxc/mxc_ipuv3_fb.c

+++ b/drivers/video/mxc/mxc_ipuv3_fb.c

@@ -48,6 +48,8 @@

#include <linux/uaccess.h>

#include <linux/fsl_devices.h>

#include <asm/mach-types.h>

+#include <mach/iomux-mx53.h>

+#include <mach/gpio.h>

/*

* Driver name

@@ -1876,6 +1878,7 @@ done:

*

* @return Appropriate error code to the kernel common code

*/

+extern struct timeval ipu_start;

static int mxcfb_probe(struct platform_device *pdev)

{

struct fb_info *fbi;

@@ -1992,8 +1995,20 @@ static int mxcfb_probe(struct platform_device *pdev)

dev_err(&pdev->dev, "Error %d on creating file\n", ret);

#ifdef CONFIG_LOGO

+ struct timeval duration;

+

fb_prepare_logo(fbi, 0);

fb_show_logo(fbi, 0);

+ mxc_iomux_v3_setup_pad(MX53_PAD_GPIO_1__PWM2_PWMO);

+

+ do_gettimeofday (&duration);

+ duration.tv_sec -= ipu_start.tv_sec;

+ duration.tv_usec -= ipu_start.tv_usec;

+ if (duration.tv_usec < 0) {

+ duration.tv_usec += 1000 * 1000;

+ duration.tv_sec -= 1;

+ }

+ printk("show log take %d s, %d us\n", duration.tv_sec, duration.tv_usec);

#endif

return 0;

4. PERCLK_ROOT requirement

There is such description in the CCM chapter of MX53 reference manual:

PERCLK_ROOT - this clock is synchronized and balanced to AHB_CLK_ROOT. For the synchronization process, peripherals clock pre-divider and post-divider should generate clock with frequency 2.5 times lower than AHB clock.

To meet this requirement, all the children clock of perclk_root should be disabled before configuring perclk_root, and enabled after configured.

If not follow this step, your kernel may hang at “Calibrating delay loop... 999.42 BogoMIPS (lpj=4997120)”.

In this kernel patch, the children of perclk_root are disabled before clk_tree_init(); then in clk_tree_init(), perclk_root is configured; and then after clk_tree_init(), pwm_clk is enabled.

Original Attachment has been moved to: u-boot.bin.zip

Original Attachment has been moved to: uImage.zip

Original Attachment has been moved to: u-boot-logo.patch.zip

Original Attachment has been moved to: kernel_bootlogo_0318.patch.zip

Screen is blank for 2 seconds between u-boot bootlogo and kernel penguin

Screen is blank for 2 seconds between u-boot bootlogo and kernel penguin

Android

i.MX53