How to realize interface Ethernet PHY with CML SGMII (has internal bias resistors 50 ohm to internal Vdd on output and input CML transistors) and P3041 SGMII - termination scheme?
AC coupled - it is clear; but:
Where place capacitor - near CML driver or near P3041 SGMII receiver?
Where place capacitor - near P3041 SGMII driver or near PHY receiver?
does I need to place additional termination resistors 50 ohm (to VDD or GND) on far end of CML driver (PHY) (double termination scheme), before capacitor, for each line (Zo=50 ohm) in pair? (Length of lines near 70-100 mm )
I'm going to simulate it, but advises very appreciated.
Thank you advance,