Shaojun Wang

Mx53 SMD u-boot PLL4 unstable issue and fix

Discussion created by Shaojun Wang Employee on Sep 21, 2012

In Mx53 SMD u-boot, when set the clock root of CKO1 to PLL4, we can observe from oscilloscope that PLL4 is not stable.

The test step is:

1. Set clock root of CKO1 to PLL4

    MX53-SMD U-Boot > mw.l 0x53fd4060 0xa00f5 1

2. Set IOMUX of GPIO_5 to CKO1

    MX53-SMD U-Boot > mw.l 0x53fa8330 3 1

3. Measure resistor R545, can see the wav is not stable.

 

Set uboot PLL4 parameter as kernel's can resolve this issue.

The patch is

 

diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c
old mode 100644
new mode 100755
index de1e388..4f795b6
--- a/cpu/arm_cortexa8/mx53/generic.c
+++ b/cpu/arm_cortexa8/mx53/generic.c
@@ -103,7 +103,7 @@ static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
        mfi = (mfi >> 4) & 0xF;
        mfi = (mfi >= 5) ? mfi : 5;

-       return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+       return ((4 * (infreq / 1000000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000000;
}

static u32 __get_mcu_main_clk(void)
diff --git a/include/asm-arm/arch-mx53/mx53.h b/include/asm-arm/arch-mx53/mx53.h
old mode 100644
new mode 100755
index 32a4c71..1dc99e7
--- a/include/asm-arm/arch-mx53/mx53.h
+++ b/include/asm-arm/arch-mx53/mx53.h
@@ -389,11 +389,15 @@
#define DP_OP_532       ((5 << 4) + ((1 - 1)  << 0))
#define DP_MFD_532      (24 - 1)
#define DP_MFN_532      13
-
+#if 0
#define DP_OP_455       ((8 << 4) + ((2 - 1)  << 0))
#define DP_MFD_455      (48 - 1)
#define DP_MFN_455      71
-
+#else
+#define DP_OP_455       ((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455      (1000000 - 1)
+#define DP_MFN_455      479166
+#endif
#define DP_OP_400       ((8 << 4) + ((2 - 1)  << 0))

 

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