AnsweredAssumed Answered

Regarding L1CSR0 register change.

Question asked by Simbu on Sep 20, 2012
Latest reply on Oct 15, 2012 by Scott Wood

Hi All,

 

I'm working on a P4 Processor(e500mc)  in which need to modify the status of the L1CSR0 register (Bit : 60) and trying the below pseudo code:

 

--> sync

--> Read from L1CSR0

--> sync

--> isync

--> Write to L1CSR0

--> isync

 

But, I could see the changes are not reflected or getting into some wierd issues (like panic and other memory related probelms). Am I missing something here? Could anyone provide pointer on this regard?

 

Thanks in Advance.

Outcomes