Wrong PLL code from CFinit!?

[Obetz]

Hello All,

IMO the MCF5213 PLL code from Coldfire INIT is somewhat strange:

1. Set CLKSRC to input clock, MFD to desired value, RFD to desired value +1 "to avoid frequency overshoot".

2. Wait for PLL lock.

3. Set correct RFD.

4. Wait _again_ for PLL lock (although it's already locked).

5. Set CLKSRC to input clock.

As far as I see, most of this is unnecessary. Since sysclock isn't affected by a "frequency overshoot", I don't care about. Certainly unnecessary is step 4, since the RFD is behind the PLL *) and doesn't affect it.

I would set CLKSRC to input clock, RFD and MFD to the desired value in a separate write operation, wait for lock and then switch to PLL clock.

Anything I'm missing?

Besides this, I would like to know whether the PLL VCO is really able to run at up to 180MHz (10MHz max. reference clock * 18).

Oliver

*) is it? The reference manual doesn't state this explicitly (as so many other details), but you can read it between the lines.

[sjmelnikoff]

Hi.

You might want to refer to the relevant section in the MCF5213 reference manual (p115, section 6.8.3, in MCF5213RM v3).

As you state, step 4 is unnecessary, and is not included in the description in the manual.

The manual suggests that the system clock could indeed be affected by overshoot if the desired RFD value were written at the same time that the clock source is switched to PLL, which could be of concern if the system clock is close to the maximum.

Regarding the maximum speed, the next section in the manual states:

The PLL can multiply the reference clock frequency by 4x to 18x, provided that the system clock frequency remains within the range listed in electrical specifications.

So I'm guessing that 180 MHz is not an option!

Steve.

[Obetz]

Hello Steve,

the procedure in the reference manual states nothing about switching sysclock to ref clock, but the INIT code does so, so you can't compare them. The INIT code is like using suspenders and belt together.

Regarding the method from the manual: I wouldn't feel good if I knew that my sysclock rides on some PLL settling transient, so I prefer to switch to refclock during a PLL change. Usually there is no time penalty since the PLL settling takes some time, anyway. Even with a 2MHz sysclock (the lowest allowed reference frequency), reading SYNSR takes only  6us. There is no benefit in "waiting faster".

The remaining question is, whether a too high frequency on the (inactive) sysclock multiplexer input hurts, or whether the RFD divider explodes while generating more than 80MHz <g>.

Regarding your guess about 180MHz, the manual says the opposite: according to the text, you _can_ multiply a 10MHz refclock by 18, that's 180MHz output from the PLL VCO. Obviously, you need to divide it with an appropriate RFD value to get an allowed sysclock.

The lower limit of the VCO output range seems to be 12MHz (3MHz * 4 or 2MHz * 6), that's a respectable 15:1 range.

Oliver

[sjmelnikoff]

Hi Oliver. In reply:

the procedure in the reference manual states nothing about switching sysclock to ref clock,

Indeed; I hadn't noticed that, as I took it as read that most people would switch to the reference clock before changing the PLL settings - in which case, as you say, it doesn't matter about clock overshoot.

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Regarding your guess about 180MHz, the manual says the opposite: according to the text, you _can_ multiply a 10MHz refclock by 18, that's 180MHz output from the PLL VCO.

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Also true, and the datasheet says nothing to the contrary.

Mind if I take back my earlier post?

Steve.