IMO the MCF5213 PLL code from Coldfire INIT is somewhat strange:
1. Set CLKSRC to input clock, MFD to desired value, RFD to desired value +1 "to avoid frequency overshoot".
2. Wait for PLL lock.
3. Set correct RFD.
4. Wait _again_ for PLL lock (although it's already locked).
5. Set CLKSRC to input clock.
As far as I see, most of this is unnecessary. Since sysclock isn't affected by a "frequency overshoot", I don't care about. Certainly unnecessary is step 4, since the RFD is behind the PLL *) and doesn't affect it.
I would set CLKSRC to input clock, RFD and MFD to the desired value in a separate write operation, wait for lock and then switch to PLL clock.
Anything I'm missing?
Besides this, I would like to know whether the PLL VCO is really able to run at up to 180MHz (10MHz max. reference clock * 18).
*) is it? The reference manual doesn't state this explicitly (as so many other details), but you can read it between the lines.