AnsweredAssumed Answered

I.MX 51 – USB unaligned memory access problem. (The USB core locks up)

Question asked by Claus Stovgaard on Aug 25, 2012
Latest reply on Mar 25, 2013 by Rohith Ramesh

I uses a custom board with an I.MX 51 and a Micron lowpower mobile DDR for memory. When developing the USB driver for a custom OS, I had a problem with the USB core not able to handle memory access correct.

The problem can be seen in the following schemes. 1 means it works, 0 means it fails. The top line is the start address for the transfer, and the left column is the length of the transfer.

length/Address0x96BA58040x96BA58050x96BA58060x96BA58070x96BA5808
102011111
102111101
102211001
102310001
102411111
length/Address0x96BA5C040x96BA5C050x96BA5C060x96BA5C070x96BA5C08
102011111
102111101
102211001
102310001
102411111

The error can be seen on instead of a 512, and 511 packet. The USB controller sends a 512 and 504 packet. And the 504 packet of cause has a wrong CRC, and the USB controller in the I.MX locks up.

First I looked more on the UOG_BURSTSIZE register. Though I was not able to change it, even though it should be RW

Thinking out of the box, I found an issue in the I.MX35 Chip Errata, ENGcm11601 USB: Core can lock up when a packet with less bytes than expected is received. It uses the SBUSCFG register on offset 0x0090. This register is not mentioned anywhere for the I.MX 51. Neither in the Reference manual or Chip Errata

Looking at this register 0x0090 in the USB core of the I.MX 51, it is set to 2. Equal INCR8, non-multiple transfers of INCR8, are decomposed into INCR4 or singles according to the I.MX 35 reference manual.

Changing this register in the I.MX 51 to 0, as proposed in the Chip Errata for the I.MX 35, it solves the issue with unaligned access. According to the I.MX 35 documentation the interface is changed to INCR burst of unspecified length.

So now the questions:

  • Has anyone else experienced problem with the USB controller and it trying to access memory unaligned, with unaligned length?
  • Is this assumption about the SBUSCFG register in the I.MX 51 correct? Is there any “secret” documentation for the I.MX 51 regarding the SBUSCFG register?
  • Does anyone know about any problems or hazards with changing the SBUSCFG register of a I.MX 51?

Thanks ahead.

Outcomes