Clocks on NE64

[WayneHowell]

Hi,

I'm using the MC9S12NE64. Initially been using the Axiom development board.

The Axiom board uses a 25MHz crystal with the internall PLL enabled. The PLL boosts to 50MHz so that the /2 internal clock is also 25MHz (or that's my understanding!)

The internal clock needs to be 25MHz for the EMAC to operate at 100BaseT.

The Axiom documentation states that 'you should not do what they are doing' because the max external bus frequency is 16MHz.

Does this actually mean that the NE64 cannot 'officially' be used with 100BaseT and the external bus enabled?

Thanks

Wayne

[DiegoNunes]

Hi Wayne,

To operate at 100Mbps, any PHY controller needs an 25MHz crystal, but NE64, only works with an 25MHz with PLL enabled.

The PHY controller uses directly the crystal clock and the MCU uses PLL clock.

If you decrase PLL ratio 5:1, EMAC Controller (in MCU) will not operate, so you will use only ethernet at 10Mbps.

In other hand, operating at PLL ratio 1:1, the MCU will work slow!

Diego

[WayneHowell]

Thanks but I'm still a little confused.

Basically I need 100BaseT, Max processor speed and an external bus.

What clock / pll settings would you recommend?

Many thanks,

Wayne

[DiegoNunes]

Wayne, you can use an 25MHz xtal and configure the PLL to 1:1ratio. The PHY controller will work at 100Mbps (or in Auto negotiation mode).
Bus Clock (PLL mode) = 2 * External Clock * (SYNR + 1) / (REFDV + 1)
Use a code link this:

void _EntryPoint(void) { // Reset Vector Interrupt
  *(byte*)INITRG_ADR = 0;              /* Set the register map position */
  asm nop;                             /* nop instruction */
  INITRM=32;                           /* Set the RAM map position */
  MISC=1;
  /* System clock initialization */
  CLKSEL=0;
  CLKSEL_PLLSEL = 0;                   /* Select clock source from XTAL */
  PLLCTL_PLLON = 0;                    /* Disable the PLL */
// Use same value to SYNR and REFV, from 0 to 15
  SYNR = 0;                           /* Set the multiplier register */
  REFDV = 0;                          /* Set the divider register */
  PLLCTL = 192;
  PLLCTL_PLLON = 1;                    /* Enable the PLL */
  while(!CRGFLG_LOCK);                 /* Wait */
  CLKSEL_PLLSEL = 1;                   /* Select clock source from PLL */

  __asm   jmp _Startup;                /* Jump to C startup code */
}


Diego

[mjbcswitzerland]

Wayne

Unfortunately you will find that it is only possible to use 10MHz with an external bus and the internal PHY.

100MHz is not possible since the external bus will have to be clocked out of specification.

It should be possible to use an external PHY at 100MHz (with its own clock), while running the NE64 with 16MHz external bus, but this means not using the main advantage of the NE64 - its internal PHY.

Personally I never use the NE64 with external bus because of this restriction. Using the Coldfire M5223X (its big brother with almost identical pin out) allows larger projects due to its 32k SRAM and 256k FLASH. This has no extension bus capabilities but it is powerful and flexible with a good range of peripherals.

This restriction has been discussed several times before - see for example
http://forums.freescale.com/freescale/board/message?board.id=16BITCOMM&message.id=548&query.id=11466...
and it seems to be confirmed to be a limitiation - unfortunately..

Regards

Mark
www.uTasker.com