Is anyone aware of how to flush the L1/L2 d-cache for a particular physical address using the set and way method (using the c7 coprocessor)? More specifically, I'd like to know the mapping between a physical address and its corresponding set/way, so that the exact slot in the cache that needs to be flushed can be specified. The ARMARM says that this mapping is implementation defined, so I'm wondering what the imx53-specific mapping is.
I'm aware that there is another method to flush a particular entry in the cache, by specifying the MVA. However, we're currently experimenting with some monitoring code in the secure world (using the TrustZone extension) where MMU is disabled, so MVA wouldn't have much meaning and therefore doesn't work. We would like to flush a particular cache slot for the normal world so that we can apply the monitor code correctly.