Ruslan S

Interval between two subsequent access on WEIM; i.MX51

Discussion created by Ruslan S on Jul 19, 2012
Latest reply on Aug 28, 2012 by Ruslan S

Hi,
We are using ConnectCore Wi-i.MX51 board with i.MX515 CPU (Windows CE 6.0, Digi BSP). We are trying to connect it to our own device as pseudo static 16-bit RAM with time write access 20 ns and time read access 30 ns.
We use WEIM engine for CS0 chip select.
We have the following access picture:
To view access cycle and other signals we used "endless" loop.

for (i=0;i<0x7FFFFFF;i++) {
OUTREG16 ( p_AsyncRAM_CSx , data16);
/* OR INREG16 ( p_AsyncRAM_CSx ); */
}

Our current register settings:

WEIM_CS0_GCR1, 0002_0081
WEIM_CS0_GCR2, 0000_0000
WEIM_CS0_RCR1, 0202_0000
WEIM_CS0_RCR2, 0000_0000
WEIM_CS0_WCR1, 0204_0040

Also CCM_Base + 0x7C |= 0033_0000

Each individual read / write access cycle is suitable.
But time interval between two subsequent access cycles is 170 ns (marked red). And it is unsuitable (must be zero).
According to settings of register WEIM_CS0_GCR1, WEIM_CS0_RCR1 and WEIM_CS0_WCR1, bits CSREC=0, RCSA=0, RCSN=0, WCSA=0, WCSN=0, this interval must be zero.

According to pictures Asynchronous Read/Write Memory Accesses Timing Diagram, Fig.63.8.3, Fig.63.8.4, Fig. 63.8.5 on page on pages 63-61(3173) - 63-64(3176) of MCIMX51RM, "MCIMX51 Multimedia Applications Processor Reference Manual", Rev. 1, 2/2010, it is possible.

How can we solve this problem?

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