PeterChan

Software defect about LCDIF clock

Discussion created by PeterChan Employee on Jul 16, 2012
Latest reply on Oct 9, 2014 by PeterChan

Dear All,

 

In MX28 BSP release L2.6.35_10.12.01, it is a software defect that the value at HW_CLKCTRL_DIS_LCDIF DIV field may be cleared by mistake when "lcdif" clock is enabled. This can lead to LCDIF malfunction. Please apply the change below to fix this problem.

 

Thanks! 

 

diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c
index 9797d1f..e732138 100644
--- a/arch/arm/mach-mx28/clock.c
+++ b/arch/arm/mach-mx28/clock.c
@@ -1199,7 +1199,7 @@ static struct clk dis_lcdif_clk = {
        .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,
        .busy_bits = 29,
        .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF,
-       .enable_bits = 31,
+       .enable_bits = BM_CLKCTRL_DIS_LCDIF_CLKGATE,
        .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
        .bypass_bits = 14,
        .get_rate = lcdif_get_rate,

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