PeterChan

Software defect about LCDIF clock

Discussion created by PeterChan Employee on Jul 16, 2012

Dear All,

 

In MX23 BSP release L2.6.31_ER_10.05.02, it is a software defect that the value at HW_CLKCTRL_PIX DIV field may be cleared by mistake when "lcdif" clock is enabled. Clearing the DIV field to 0 can lead to LCDIF malfunction. Please apply the change below to fix this problem.

 

Thanks! 

 

diff --git a/arch/arm/mach-mx23/clock.c b/arch/arm/mach-mx23/clock.c
index a4de6d5..8f20117 100644
--- a/arch/arm/mach-mx23/clock.c
+++ b/arch/arm/mach-mx23/clock.c
@@ -498,7 +498,7 @@ static struct clk lcdif_clk = {
.busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
.busy_bits = 29,
.enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
- .enable_bits = 31,
+ .enable_bits = BM_CLKCTRL_PIX_CLKGATE,
.bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
.bypass_bits = 1,
.get_rate = lcdif_get_rate,

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