Tim Hawkins

PCB layout of DDR3

Discussion created by Tim Hawkins on Jun 27, 2012
Latest reply on Jul 4, 2012 by Jose Nicolas Izquierdo Martinez


I'm using an iMX53 and I have designed for two DDR3 chips of 2Gb (128M-bit x 16) giving a total of 512MBytes of RAM.

My question is on how to lay out the PCB.

The CPU has the ability to do read and write leveling which means I can use a "fly-by" topology.  But, because i'm using only two RAM chips i'm thinking that it would be far easier to use a balanced line or tree type topology that i would use on DDR2.

What would you advise?