Hello,
In the MCU, there is a global interrupt mask available.
Out of Reset, all Interrupts are masked (temporarily disabled, but the interrupt stays pending).
This mask is the I bit in the CCR = Condition Code Register.
Enable interrupts is Clearing the bit while disabling interrupts set the bit.
These functions are just doing a
asm CLI or
asm SEI, the assembly instruction to enable/disable the global mask.
You still have to handle local enable of interrupts in all the modules. For the CAN, I think it is in CANIER, CANRIER and CANTIER, or with a similar name. They are explained in the msCAN block guide.
The I bit is described in the CPU reference manual.
Cheers,
Alban.