yekta ayduk

DDR2 HW ZQ Calibration

Discussion created by yekta ayduk on Jun 12, 2012
Latest reply on Jan 17, 2013 by Yuri Muhin

Hi Community Members

I checked the DRAM_SDCKL_P and DRAM_SDCLK_N  signals in my HW ( no u-boot prompt) ,
the DC level of these signals should be VDDQ/2=Vref=0.9V , but I measured about 1.25Vdc.

Then I found an application note AN4466:imx53 DDR Calibration .Which says:

"Altough ODT activation is not typical for DDR2 ,it should be noted that ZQ calibration is recommended for setting the right bias for the DDR2 signals"

On another page : "Calibration sequence should be executed after the DDR memory has been initialized."

The DDR init code is in flash_header.S .
 I have to start the calibration by setting a bit of the ZQ ESDCTL register and wait until HW clears this bit(calibration done).

I dont know how to add this into flash_header.S.

Does  anybody know  any board example which uses DDR Calibration sequence ?
Or does anybody want to share his/her solution?

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