yekta ayduk

DDR3 SDRAM pins are shuffeled?

Discussion created by yekta ayduk on May 25, 2012
Latest reply on Jun 25, 2012 by Yuri Muhin


In the schematics of one of the reference design four 2G_DDR3 (128x16) chips are used.

I realised that the DQ0-DQ15 pins are not connected to the DRAM_D0-DRAM_D15 Bus and
DRAM_D16-DRAM_D31 Bus in the numerical order.

High Byte Pins are shuffeled and Low byte pins are shuffeled .

I suppose these pins are swapped to be able to make the layout connections easily.

What do you think?