udaya kumar

DDR3 CLK termination

Discussion created by udaya kumar on May 21, 2012
Latest reply on Jun 6, 2012 by Tomotaka Inamura

Hi,
We are in the rudimentary stage of Schemtic design of i.MX535 .DDR3 clock lines has been terminated with 200 ohm res in the ref schematic of Sabre.

Question is , In general, differential clock will be terminated by 100 ohm . Can anyone explain, why they double the resistor value in Sabre design?

Regards,

UKR

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