positron positron

I.Mx SDRAM interfacing

Discussion created by positron positron on May 1, 2012

In the MX53SUG.pdf the explanation for DDR_INPUT field in the IOMUX chapter is this,

"DDR_INPUT (1 bit ddr_input control)—Needed when interfacing DDR memories."

 

But nowhere it is mentioned whether or not to enable this bit? And to which pins this should be enabled?

Any ideas on what is the CMOS input mode and Differential input mode?

 



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