i.MX51 eSDHC issue -blog archive

Discussion created by LinWang Employee on Apr 15, 2012

The cmd complete and cmd error are asserted at same cycle in sd_clk domain. These 2 signals need be synced to ipg_clk domain to be stored in IRQSTAT reigster. It is possible that the synced cmd complete signal wound be one cycle earlier than synced cmd error signal in some special voltage or temperature. If it happens, sometimes SW would read only cmd complete signal in IRQSTAT reigster. And after one ipg cycle, the cmd timeout error can be read in IRQSTAT reigster.