Joseph Stepien

MCF52233 DEMO Interrupt Priorities and Levels

Discussion created by Joseph Stepien on May 16, 2007
Latest reply on Jun 15, 2007 by Bryan Kattwinkel
Hi,
 
I've been working with the DEMO board for a bit now and I've noticed that the code has assigned the same Interrupt Priority and Level to a number of interrupts.  This is expressly forbidden according to documentation, see below.  I only discovered this after indeed seeing some undefined behaviour with respect to interrupts.  This seems like a very elementary mistake as we came across this problem previously for a 5213 ColdFire.   Providing unique and non-overlapping level and priority definitions avoided the undefined behaviour in 5213 and I'm hoping same is true of 52233.  Has anyone else caught this error?
 

15.3.6 Interrupt Control Register (ICRnx)

Each ICRnx, where x equals 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level

(0–7). All ICRnx registers can be read, but only ICRn8 to ICRn63 can be written. It is the responsibility

of the software to program the ICRnx registers with unique and non-overlapping level and priority

definitions. Failure to program the ICRnx registers in this manner can result in undefined behavior. If a

specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state

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