Marc Coussement

Bug in IMX28 WINCE BSP NAND interface

Discussion created by Marc Coussement on Mar 8, 2012
Latest reply on Mar 12, 2012 by fear_nada

hi all,

I found and solved a very nasty bug in the IMX28 WINCE BSP initialization code for the NAND flash interface.

The RDN (read) signal is faulty driven by 1V8 signal level all other signals to the NAND have 3V3 signal levels. With this some NAND device will give read errors as the spec is 70% of VCC gives 2V4 as specification for high signal.

The prototype of the function in source

“C:\WINCE600\PLATFORM\COMMON\SRC\SOC\MX28_FSL_V2_PDK1_9\INC\mx28_ddk.h”

BOOL DDKIomuxSetPadConfig(DDK_IOMUX_PIN pin,
DDK_IOMUX_PAD_DRIVE drive,
DDK_IOMUX_PAD_PULL pull,
DDK_IOMUX_PAD_VOLTAGE voltage)

The enum type to set the voltage of the outputs in source

“C:\WINCE600\PLATFORM\COMMON\SRC\SOC\MX28_FSL_V2_PDK1_9\INC\mx28_ddk.h”

typedef enum
{
DDK_IOMUX_PAD_VOLTAGE_RESERVED = 0,
DDK_IOMUX_PAD_VOLTAGE_1V8 = 0,
DDK_IOMUX_PAD_VOLTAGE_3V3 = 1
} DDK_IOMUX_PAD_VOLTAGE;

The Faulty code line in source “C:\WINCE600\PLATFORM\iMX28-EVK-PDK1_9\SRC\COMMON\NANDFMD\nandbsp.cpp”

// Set the pin drive for the RDN pin to 8mA.
DDKIomuxSetPadConfig(DDK_IOMUX_GPMI_RDN,DDK_IOMUX_PAD_DRIVE_8MA,(DDK_IOMUX_PAD_PULL)0,(DDK_IOMUX_PAD_VOLTAGE)0);

The Change I made

DDKIomuxSetPadConfig(DDK_IOMUX_GPMI_RDN,DDK_IOMUX_PAD_DRIVE_8MA,(DDK_IOMUX_PAD_PULL)0,DDK_IOMUX_PAD_VOLTAGE_3V3);

The strange about this is, the programmer made a nice enum type for the voltage of the outputs, but is not using the enum type in the function call. The programmer did use a cast of a numeric “0” value ???!!!

 

I have a call for help to the community for the following:

There is still one question about timing:

The Micron “MT29F8G08ABABA” has different timing modes (mode 0 tot mode 5) after reset the nand starts with default timing “mode 0” this is a very slow timing with read cycles of 100ns.
The chip can be set to another timing mode by writing into the “feature” register. I don‘t have an example of a DMA sequence to write into the “feature register”. 

The sequence is

<Command><Adress> <DataIn><DataIn><DataIn><DataIn>

This is different than the program page sequence  

<Command> <Adress> <Adress> <Adress> <Adress> <Adress> <DataIn><DataIn><DataIn><DataIn> ... <Command>

help is appreciated

Marc Coussement

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