Marko Panger

PMC counters not working (was: oprofile not working)

Discussion created by Marko Panger on Feb 10, 2012
Latest reply on Jun 20, 2014 by Maarten Blomme

Hi all,

I've already posted a similar post in the i.MX53 group. It was about oprofile not generating events other than CPU CYCLES (i.e no CACHE MISS,...) To summarize my problem was that oprofile was not working for me. After following a tutorial ( to add the PMU (ARM Performance Monutor Unit) device to the linux kernel I still wasn't able to get any reading from the PMU counters. The only exception was the "CPU CYCLES" counter.

According to the Cortex-A8 Technical Reference Manual ( the performance counters are enabled if DBGEN signal is set to 1 (see table 3.99). Now, this signal is SOC (Freescale in this case) specific.

I've searched the i.MX53 Reference Manual and on p.624 found the ARM_GPC register which contains the DBGEN enable bit. I've set this bit via the 'linux/arch/arm/mach-mx5/cpu.c' cpu file:

    #define CORTEXA8_PLAT_GPC    0x04

    arm_plat_base = ioremap(MX53_BASE_ADDR(ARM_BASE_ADDR), SZ_4K);
    reg = __raw_readl(arm_plat_base + CORTEXA8_PLAT_GPC);
    printk(KERN_DEBUG "CORTEXA8_PLAT_GPC: %u\n", reg);
    reg |= (1 16); //set DBGEN to 1
    __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_GPC);

    reg = __raw_readl(arm_plat_base + CORTEXA8_PLAT_GPC);
    printk(KERN_DEBUG "CORTEXA8_PLAT_GPC: %u\n", reg);

However after this modification I'm still unable to get any performance counter reading out of PMC. To eliminate the oprofile factor (could have a bug on this platform) I wrote few line to manually access the PMC. The resoult is always the same. I'm able to get cycle counter but no performace couter reading.

A similar bug was reported here:

Any ideas ? Maybe someone from Freescale could take a look ?

Thanks, Marko